Educational guide School of Engineering |
english |
Engineering and Technology of Electronic Systems (2014) |
Subjects |
ADVANCED DIGITAL SYSTEMS |
Contents |
IDENTIFYING DATA | 2017_18 |
Subject | ADVANCED DIGITAL SYSTEMS | Code | 17675103 | |||||
Study programme |
|
Cycle | 2nd | |||||
Descriptors | Credits | Type | Year | Period | ||||
4 | Compulsory | First | 1Q |
Competences | Learning outcomes | Contents |
Planning | Methodologies | Personalized attention |
Assessment | Sources of information | Recommendations |
Topic | Sub-topic |
Introducction to FPGAs | General architecture Xilinx Spartan-6 |
VHDL Synthesis | Design flow Entity and architecture Libraries and packages STD y IEEE. Data types RTL description Structural description Behavioral description VHDL synthesis |
Xilinx System Generator Synthesis | Design flow Representation of real numbers with fixed-point codification Simulink blocks |