| Educational guide School of Engineering |
english |
| Bachelor's Degree in Computer engineering (2010) |
 Subjects |
| COMPUTER ARCHITECTURE |
 
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| IDENTIFYING DATA | 2015_16 | |||||||||||||||||
| Subject (*) | COMPUTER ARCHITECTURE | Code | 17234109 | |||||||||||||||
| Study programme |
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Cycle | 1st | |||||||||||||||
| Descriptors | Credits | Type | Year | Period | Exam timetables and dates | |||||||||||||
| 6 | Compulsory | Third | 1Q |
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| Modality and teaching language | See working groups | |||||||||||||||||
| Prerequisites | ||||||||||||||||||
| Department | Enginyeria Informàtica i Matemàtiques |
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| Coordinator |
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carles.aliagas@urv.cat carlos.molina@urv.cat |
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| Lecturers |
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| Web | http://moodle.urv.net | |||||||||||||||||
| General description and relevant information | This course aims to introduce students into the design, implementation and evaluation of superscalar processors and parallel systems. | |||||||||||||||||
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| (*)The teaching guide is the document in which the URV publishes the information about all its courses. It is a public document and cannot be modified. Only in exceptional cases can it be revised by the competent agent or duly revised so that it is in line with current legislation. | ||||||||||||||||||
