| Educational guide School of Engineering |
english |
| Electric Vehicle Technologies (2018) |
 Subjects |
| DESIGN OF DIGITAL SYSTEMS WITH FPGA |
| Contents |
| IDENTIFYING DATA | 2018_19 |
| Subject | DESIGN OF DIGITAL SYSTEMS WITH FPGA | Code | 17695103 | |||||
| Study programme |
|
Cycle | 2nd | |||||
| Descriptors | Credits | Type | Year | Period | ||||
| 3 | Compulsory | First | 1Q |
|||||
| Competences | Learning outcomes | Contents |
| Planning | Methodologies | Personalized attention |
| Assessment | Sources of information | Recommendations |
| Topic | Sub-topic |
| Introducction to FPGAs | Overview Spantan-6 architecture: CLB, Routing resources, I/O resources, BRAM, DSP |
| VHDL for synthesis | Design flow: functional, post-synthesis and post-layout simulation Entity, architecture, package, package body Testbench Libraries: WORK, STD, IEEE MLV9 RTL, behavioural & structural descriptions Constants, signals and variables VHDL Simulation and delta delay Assertions |
